105 lines
2.9 KiB
Plaintext
105 lines
2.9 KiB
Plaintext
(version 1)
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(rule "Track width, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.1mm))
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)
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(rule "Track spacing, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.1mm))
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)
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(rule "Track width, inner layer"
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(layer inner)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.09mm))
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)
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(rule "Track spacing, inner layer"
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.09mm))
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)
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(rule "Silkscreen text"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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)
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(rule "Pad to Silkscreen"
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(layer outer)
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(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
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(constraint silk_clearance (min 0.15mm))
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)
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(rule "Edge (routed) to track clearance"
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(condition "A.Type == 'track'")
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(constraint edge_clearance (min 0.3mm))
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)
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(rule "Hole diameter"
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(constraint hole_size (min 0.15mm) (max 6.3mm))
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)
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(rule "Hole (NPTH) diameter"
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(layer outer)
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(condition "!A.isPlated()")
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(constraint hole_size (min 0.5mm))
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)
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# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
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(rule "Hole (castellated) diameter"
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(layer outer)
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
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(constraint hole_size (min 0.5mm))
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)
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# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
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# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
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(rule "Annular ring width (via and PTH)"
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(layer outer)
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(condition "A.isPlated()")
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(constraint annular_width (min 0.05mm))
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)
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(rule "Clearance: hole to hole (perimeter), different nets"
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(layer outer)
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(condition "A.Net != B.Net")
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(constraint hole_to_hole (min 0.45mm))
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)
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(rule "Clearance: hole to hole (perimeter), same net"
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(layer outer)
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(condition "A.Net == B.Net")
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(constraint hole_to_hole (min 0.2mm))
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)
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(rule "Clearance: track to NPTH hole (perimeter)"
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# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
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(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.254mm))
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)
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(rule "Clearance: track to PTH hole perimeter"
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(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.33mm))
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)
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# TODO: try combining with rule "Clearance: PTH to track, different nets"
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(rule "Clearance: track to pad"
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(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
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(constraint clearance (min 0.1mm))
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)
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(rule "Clearance: pad/via to pad/via"
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(layer outer)
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# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
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(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
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(constraint clearance (min 0.1mm))
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)
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