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New PCB for FCB1010

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This commit is contained in:
Geens 2025-06-01 14:24:00 +02:00
parent 1bc1224441
commit a12c77354b
61 changed files with 99039 additions and 0 deletions
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4
.gitignore vendored
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@ -1 +1,5 @@
*-backups/
*.bak
*.zip
/target
fp-info-cache

2
FCB1010/FCB1010/FCB1010.kicad_pcb Normal file
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(kicad_pcb (version 20241229) (generator "pcbnew") (generator_version "9.0")
)

78
FCB1010/FCB1010/FCB1010.kicad_prl Normal file
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{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"shapes": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"git": {
"repo_type": "",
"repo_username": "",
"ssh_key": ""
},
"meta": {
"filename": "FCB1010.kicad_prl",
"version": 3
},
"net_inspector_panel": {
"col_hidden": [],
"col_order": [],
"col_widths": [],
"custom_group_rules": [],
"expanded_rows": [],
"filter_by_net_name": true,
"filter_by_netclass": true,
"filter_text": "",
"group_by_constraint": false,
"group_by_netclass": false,
"show_unconnected_nets": false,
"show_zero_pad_nets": false,
"sort_ascending": true,
"sorting_column": -1
},
"open_jobsets": [],
"project": {
"files": []
},
"schematic": {
"selection_filter": {
"graphics": true,
"images": true,
"labels": true,
"lockedItems": false,
"otherItems": true,
"pins": true,
"symbols": true,
"text": true,
"wires": true
}
}
}

411
FCB1010/FCB1010/FCB1010.kicad_pro Normal file
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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {},
"track_widths": [],
"via_dimensions": []
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_pairs": [],
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "FCB1010.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "${PROJECTNAME}.csv",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
},
{
"group_by": true,
"label": "Exclude from BOM",
"name": "${EXCLUDE_FROM_BOM}",
"show": true
},
{
"group_by": true,
"label": "Exclude from Board",
"name": "${EXCLUDE_FROM_BOARD}",
"show": true
},
{
"group_by": true,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"include_excluded_from_bom": true,
"name": "Default Editing",
"sort_asc": true,
"sort_field": "Referentie"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"space_save_all_events": true,
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"a390f433-03f2-4395-80f3-6c0b98700305",
"Root"
]
],
"text_variables": {}
}

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FCB1010/FCB1010/FCB1010.kicad_sch Normal file
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FCB1010/FCB1010/datasheets/74HC273D.pdf Normal file
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FCB1010/FCB1010/datasheets/74HC_HCT04.pdf Normal file
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FCB1010/FCB1010/datasheets/80C31_80C32.pdf Normal file
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FCB1010/FCB1010/datasheets/KM62256C.pdf Normal file
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FCB1010/FCB1010/datasheets/W78C32C.pdf Normal file
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FCB1010/FCB1010/datasheets/tl7705a.pdf Normal file
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FCB1010/FCB1010/datasheets/tlc0832.pdf Normal file
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7
FCB1010/FCB1010_controller/BOM.csv Normal file
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"Comment","Designator","Footprint","LCSC part number"
"Cap 0402 100nF 10V","C1,C2,C3,C4,C7","CL05:C_0402","C133086"
"Cap 0402 1uF 10V","C5,C6","CL05:C_0402","C14445"
"Pin Header 2X4 1.27mm SMD","J1","XKB:X1321WVS-2x04J-C40D53","C2881909"
"STM32F042C6T6","U1","STM32F042C6T6:QFP50P700X700X160-48N","C88447"
"TXU0104RUTR","U2,U3,U4,U5","TXU0104RUTR:PQFP12_RUT_TEX","C5187176"
"LDO 3V3 600mA","U6","AP2112K-3.3TRG1:SOT_RG1_DIO","C51118"
1 Comment Designator Footprint LCSC part number
2 Cap 0402 100nF 10V C1,C2,C3,C4,C7 CL05:C_0402 C133086
3 Cap 0402 1uF 10V C5,C6 CL05:C_0402 C14445
4 Pin Header 2X4 1.27mm SMD J1 XKB:X1321WVS-2x04J-C40D53 C2881909
5 STM32F042C6T6 U1 STM32F042C6T6:QFP50P700X700X160-48N C88447
6 TXU0104RUTR U2,U3,U4,U5 TXU0104RUTR:PQFP12_RUT_TEX C5187176
7 LDO 3V3 600mA U6 AP2112K-3.3TRG1:SOT_RG1_DIO C51118

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FCB1010/FCB1010_controller/FCB1010_controller.kicad_dru Normal file
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(version 1)
(rule "Track width, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track'")
(constraint track_width (min 0.1mm))
)
(rule "Track spacing, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.1mm))
)
(rule "Track width, inner layer"
(layer inner)
(condition "A.Type == 'track'")
(constraint track_width (min 0.09mm))
)
(rule "Track spacing, inner layer"
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.09mm))
)
(rule "Silkscreen text"
(layer "?.Silkscreen")
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
)
(rule "Pad to Silkscreen"
(layer outer)
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
(constraint silk_clearance (min 0.15mm))
)
(rule "Edge (routed) to track clearance"
(condition "A.Type == 'track'")
(constraint edge_clearance (min 0.3mm))
)
(rule "Hole diameter"
(constraint hole_size (min 0.15mm) (max 6.3mm))
)
(rule "Hole (NPTH) diameter"
(layer outer)
(condition "!A.isPlated()")
(constraint hole_size (min 0.5mm))
)
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Hole (castellated) diameter"
(layer outer)
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
(constraint hole_size (min 0.5mm))
)
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Annular ring width (via and PTH)"
(layer outer)
(condition "A.isPlated()")
(constraint annular_width (min 0.05mm))
)
(rule "Clearance: hole to hole (perimeter), different nets"
(layer outer)
(condition "A.Net != B.Net")
(constraint hole_to_hole (min 0.45mm))
)
(rule "Clearance: hole to hole (perimeter), same net"
(layer outer)
(condition "A.Net == B.Net")
(constraint hole_to_hole (min 0.2mm))
)
(rule "Clearance: track to NPTH hole (perimeter)"
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.254mm))
)
(rule "Clearance: track to PTH hole perimeter"
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.33mm))
)
# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Clearance: track to pad"
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
(constraint clearance (min 0.1mm))
)
(rule "Clearance: pad/via to pad/via"
(layer outer)
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
(constraint clearance (min 0.1mm))
)

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FCB1010/FCB1010_controller/FCB1010_controller.kicad_pcb Normal file
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FCB1010/FCB1010_controller/FCB1010_controller.kicad_prl Normal file
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{
"board": {
"active_layer": 5,
"active_layer_preset": "",
"auto_track_width": false,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"shapes": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 1.0
},
"selection_filter": {
"dimensions": false,
"footprints": false,
"graphics": false,
"keepouts": false,
"lockedItems": false,
"otherItems": false,
"pads": false,
"text": true,
"tracks": false,
"vias": false,
"zones": false
},
"visible_items": [
"vias",
"footprint_text",
"footprint_anchors",
"ratsnest",
"grid",
"footprints_front",
"footprints_back",
"footprint_values",
"footprint_references",
"tracks",
"drc_errors",
"drawing_sheet",
"bitmaps",
"pads",
"zones",
"drc_warnings",
"locked_item_shadows",
"conflict_shadows",
"shapes"
],
"visible_layers": "00000000_00000000_55555555_57555521",
"zone_display_mode": 0
},
"git": {
"repo_type": "",
"repo_username": "",
"ssh_key": ""
},
"meta": {
"filename": "FCB1010_controller.kicad_prl",
"version": 5
},
"net_inspector_panel": {
"col_hidden": [
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false
],
"col_order": [
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"col_widths": [
162,
147,
91,
76,
91,
91,
91,
67,
91,
91,
91,
91
],
"custom_group_rules": [],
"expanded_rows": [],
"filter_by_net_name": true,
"filter_by_netclass": true,
"filter_text": "",
"group_by_constraint": false,
"group_by_netclass": false,
"show_unconnected_nets": false,
"show_zero_pad_nets": false,
"sort_ascending": true,
"sorting_column": 0
},
"open_jobsets": [],
"project": {
"files": []
},
"schematic": {
"selection_filter": {
"graphics": true,
"images": true,
"labels": true,
"lockedItems": false,
"otherItems": true,
"pins": true,
"symbols": true,
"text": true,
"wires": true
}
}
}

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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": true,
"text_position": 0,
"units_format": 0
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.5,
"height": 1.0,
"width": 1.0
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.1
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "ignore",
"extra_footprint": "ignore",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_to_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "ignore",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore",
"missing_footprint": "ignore",
"net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
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"Comment","Designator","Footprint","LCSC part number"
"Cap 0402 100nF 10V","C1,C2,C3,C4,C7","CL05:C_0402","C133086"
"Cap 0402 1uF 10V","C5,C6","CL05:C_0402","C14445"
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"LDO 3V3 600mA","U6","AP2112K-3.3TRG1:SOT_RG1_DIO","C51118"
1 Comment Designator Footprint LCSC part number
2 Cap 0402 100nF 10V C1,C2,C3,C4,C7 CL05:C_0402 C133086
3 Cap 0402 1uF 10V C5,C6 CL05:C_0402 C14445
4 Pin Header 2X4 1.27mm SMD J1 XKB:X1321WVS-2x04J-C40D53 C2881909
5 STM32F042C6T6 U1 STM32F042C6T6:QFP50P700X700X160-48N C88447
6 TXU0104RUTR U2,U3,U4,U5 TXU0104RUTR:PQFP12_RUT_TEX C5187176
7 LDO 3V3 600mA U6 AP2112K-3.3TRG1:SOT_RG1_DIO C51118

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%TF.FileFunction,Soldermask,Top*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 9.0.2) date 2025-06-01 13:38:19*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10R,0.740000X2.400000*%
%ADD11RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*%
%ADD12RoundRect,0.140000X0.140000X0.170000X-0.140000X0.170000X-0.140000X-0.170000X0.140000X-0.170000X0*%
%ADD13R,0.203200X0.863600*%
%ADD14R,0.863600X0.203200*%
%ADD15C,1.000000*%
%ADD16R,0.508000X1.003300*%
%ADD17RoundRect,0.140000X0.690000X0.060000X-0.690000X0.060000X-0.690000X-0.060000X0.690000X-0.060000X0*%
%ADD18RoundRect,0.140000X0.060000X0.690000X-0.060000X0.690000X-0.060000X-0.690000X0.060000X-0.690000X0*%
G04 APERTURE END LIST*
D10*
%TO.C,J1*%
X156705000Y-102550000D03*
X156705000Y-106450000D03*
X155435000Y-102550000D03*
X155435000Y-106450000D03*
X154165000Y-102550000D03*
X154165000Y-106450000D03*
X152895000Y-102550000D03*
X152895000Y-106450000D03*
%TD*%
D11*
%TO.C,C7*%
X153400000Y-97820000D03*
X153400000Y-98780000D03*
%TD*%
D12*
%TO.C,C6*%
X156680000Y-97300000D03*
X155720000Y-97300000D03*
%TD*%
%TO.C,C5*%
X152480000Y-93000000D03*
X151520000Y-93000000D03*
%TD*%
D11*
%TO.C,C4*%
X153400000Y-95820000D03*
X153400000Y-96780000D03*
%TD*%
%TO.C,C3*%
X143500000Y-102020000D03*
X143500000Y-102980000D03*
%TD*%
%TO.C,C2*%
X151500000Y-102020000D03*
X151500000Y-102980000D03*
%TD*%
D12*
%TO.C,C1*%
X143480000Y-92800000D03*
X142520000Y-92800000D03*
%TD*%
D13*
%TO.C,U2*%
X147800001Y-104725300D03*
X147399999Y-104725300D03*
X147000000Y-104725300D03*
X146600001Y-104725300D03*
X146199999Y-104725300D03*
D14*
X146072900Y-105500000D03*
D13*
X146199999Y-106274700D03*
X146600001Y-106274700D03*
X147000000Y-106274700D03*
X147399999Y-106274700D03*
X147800001Y-106274700D03*
D14*
X147927100Y-105500000D03*
%TD*%
D13*
%TO.C,U3*%
X150900001Y-104725300D03*
X150499999Y-104725300D03*
X150100000Y-104725300D03*
X149700001Y-104725300D03*
X149299999Y-104725300D03*
D14*
X149172900Y-105500000D03*
D13*
X149299999Y-106274700D03*
X149700001Y-106274700D03*
X150100000Y-106274700D03*
X150499999Y-106274700D03*
X150900001Y-106274700D03*
D14*
X151027100Y-105500000D03*
%TD*%
D15*
%TO.C,BRD1*%
X150000000Y-91700000D03*
X148730000Y-91700000D03*
X147460000Y-91700000D03*
X146190000Y-91700000D03*
X144920000Y-91700000D03*
X143650000Y-91700000D03*
X141700000Y-93650000D03*
X141700000Y-94920000D03*
X141700000Y-96190000D03*
X141700000Y-97460000D03*
X141700000Y-98730000D03*
X141700000Y-100000000D03*
X141700000Y-101270000D03*
X141700000Y-102540000D03*
X141700000Y-103810000D03*
X141700000Y-105080000D03*
X141700000Y-106350000D03*
X143650000Y-108300000D03*
X144920000Y-108300000D03*
X146190000Y-108300000D03*
X147460000Y-108300000D03*
X148730000Y-108300000D03*
X150000000Y-108300000D03*
X151270000Y-108300000D03*
X152540000Y-108300000D03*
X153810000Y-108300000D03*
X155080000Y-108300000D03*
X156350000Y-108300000D03*
X158300000Y-106350000D03*
X158300000Y-105080000D03*
X158300000Y-103810000D03*
X158300000Y-102540000D03*
X158300000Y-101270000D03*
X158300000Y-100000000D03*
X158300000Y-98730000D03*
X158300000Y-97460000D03*
X158300000Y-96190000D03*
X158300000Y-94920000D03*
X158300000Y-93650000D03*
X156350000Y-91700000D03*
X155080000Y-91700000D03*
X153810000Y-91700000D03*
X152540000Y-91700000D03*
X151270000Y-91700000D03*
%TD*%
D13*
%TO.C,U4*%
X144700001Y-104725300D03*
X144299999Y-104725300D03*
X143900000Y-104725300D03*
X143500001Y-104725300D03*
X143099999Y-104725300D03*
D14*
X142972900Y-105500000D03*
D13*
X143099999Y-106274700D03*
X143500001Y-106274700D03*
X143900000Y-106274700D03*
X144299999Y-106274700D03*
X144700001Y-106274700D03*
D14*
X144827100Y-105500000D03*
%TD*%
%TO.C,U5*%
X154725300Y-98599999D03*
X154725300Y-99000001D03*
X154725300Y-99400000D03*
X154725300Y-99799999D03*
X154725300Y-100200001D03*
D13*
X155500000Y-100327100D03*
D14*
X156274700Y-100200001D03*
X156274700Y-99799999D03*
X156274700Y-99400000D03*
X156274700Y-99000001D03*
X156274700Y-98599999D03*
D13*
X155500000Y-98472900D03*
%TD*%
D16*
%TO.C,U6*%
X156750001Y-93147450D03*
X155800000Y-93147450D03*
X154849999Y-93147450D03*
X154849999Y-95852550D03*
X156750001Y-95852550D03*
%TD*%
D17*
%TO.C,U1*%
X151680000Y-100250000D03*
X151680000Y-99750000D03*
X151680000Y-99250000D03*
X151680000Y-98750000D03*
X151680000Y-98250000D03*
X151680000Y-97750000D03*
X151680000Y-97250000D03*
X151680000Y-96750000D03*
X151680000Y-96250000D03*
X151680000Y-95750000D03*
X151680000Y-95250000D03*
X151680000Y-94750000D03*
D18*
X150250000Y-93320000D03*
X149750000Y-93320000D03*
X149250000Y-93320000D03*
X148750000Y-93320000D03*
X148250000Y-93320000D03*
X147750000Y-93320000D03*
X147250000Y-93320000D03*
X146750000Y-93320000D03*
X146250000Y-93320000D03*
X145750000Y-93320000D03*
X145250000Y-93320000D03*
X144750000Y-93320000D03*
D17*
X143320000Y-94750000D03*
X143320000Y-95250000D03*
X143320000Y-95750000D03*
X143320000Y-96250000D03*
X143320000Y-96750000D03*
X143320000Y-97250000D03*
X143320000Y-97750000D03*
X143320000Y-98250000D03*
X143320000Y-98750000D03*
X143320000Y-99250000D03*
X143320000Y-99750000D03*
X143320000Y-100250000D03*
D18*
X144750000Y-101680000D03*
X145250000Y-101680000D03*
X145750000Y-101680000D03*
X146250000Y-101680000D03*
X146750000Y-101680000D03*
X147250000Y-101680000D03*
X147750000Y-101680000D03*
X148250000Y-101680000D03*
X148750000Y-101680000D03*
X149250000Y-101680000D03*
X149750000Y-101680000D03*
X150250000Y-101680000D03*
%TD*%
M02*

217
FCB1010/FCB1010_controller/gerber/FCB1010_controller-F_Paste.gbr Normal file
View File

@ -0,0 +1,217 @@
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.2*%
%TF.CreationDate,2025-06-01T13:38:18+02:00*%
%TF.ProjectId,FCB1010_controller,46434231-3031-4305-9f63-6f6e74726f6c,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Paste,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 9.0.2) date 2025-06-01 13:38:18*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10R,0.740000X2.400000*%
%ADD11RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*%
%ADD12RoundRect,0.140000X0.140000X0.170000X-0.140000X0.170000X-0.140000X-0.170000X0.140000X-0.170000X0*%
%ADD13R,0.203200X0.863600*%
%ADD14R,0.863600X0.203200*%
%ADD15R,0.508000X1.003300*%
%ADD16RoundRect,0.105000X0.675000X0.045000X-0.675000X0.045000X-0.675000X-0.045000X0.675000X-0.045000X0*%
%ADD17RoundRect,0.105000X0.045000X0.675000X-0.045000X0.675000X-0.045000X-0.675000X0.045000X-0.675000X0*%
G04 APERTURE END LIST*
D10*
%TO.C,J1*%
X156705000Y-102550000D03*
X156705000Y-106450000D03*
X155435000Y-102550000D03*
X155435000Y-106450000D03*
X154165000Y-102550000D03*
X154165000Y-106450000D03*
X152895000Y-102550000D03*
X152895000Y-106450000D03*
%TD*%
D11*
%TO.C,C7*%
X153400000Y-97820000D03*
X153400000Y-98780000D03*
%TD*%
D12*
%TO.C,C6*%
X156680000Y-97300000D03*
X155720000Y-97300000D03*
%TD*%
%TO.C,C5*%
X152480000Y-93000000D03*
X151520000Y-93000000D03*
%TD*%
D11*
%TO.C,C4*%
X153400000Y-95820000D03*
X153400000Y-96780000D03*
%TD*%
%TO.C,C3*%
X143500000Y-102020000D03*
X143500000Y-102980000D03*
%TD*%
%TO.C,C2*%
X151500000Y-102020000D03*
X151500000Y-102980000D03*
%TD*%
D12*
%TO.C,C1*%
X143480000Y-92800000D03*
X142520000Y-92800000D03*
%TD*%
D13*
%TO.C,U2*%
X147800001Y-104725300D03*
X147399999Y-104725300D03*
X147000000Y-104725300D03*
X146600001Y-104725300D03*
X146199999Y-104725300D03*
D14*
X146072900Y-105500000D03*
D13*
X146199999Y-106274700D03*
X146600001Y-106274700D03*
X147000000Y-106274700D03*
X147399999Y-106274700D03*
X147800001Y-106274700D03*
D14*
X147927100Y-105500000D03*
%TD*%
D13*
%TO.C,U3*%
X150900001Y-104725300D03*
X150499999Y-104725300D03*
X150100000Y-104725300D03*
X149700001Y-104725300D03*
X149299999Y-104725300D03*
D14*
X149172900Y-105500000D03*
D13*
X149299999Y-106274700D03*
X149700001Y-106274700D03*
X150100000Y-106274700D03*
X150499999Y-106274700D03*
X150900001Y-106274700D03*
D14*
X151027100Y-105500000D03*
%TD*%
D13*
%TO.C,U4*%
X144700001Y-104725300D03*
X144299999Y-104725300D03*
X143900000Y-104725300D03*
X143500001Y-104725300D03*
X143099999Y-104725300D03*
D14*
X142972900Y-105500000D03*
D13*
X143099999Y-106274700D03*
X143500001Y-106274700D03*
X143900000Y-106274700D03*
X144299999Y-106274700D03*
X144700001Y-106274700D03*
D14*
X144827100Y-105500000D03*
%TD*%
%TO.C,U5*%
X154725300Y-98599999D03*
X154725300Y-99000001D03*
X154725300Y-99400000D03*
X154725300Y-99799999D03*
X154725300Y-100200001D03*
D13*
X155500000Y-100327100D03*
D14*
X156274700Y-100200001D03*
X156274700Y-99799999D03*
X156274700Y-99400000D03*
X156274700Y-99000001D03*
X156274700Y-98599999D03*
D13*
X155500000Y-98472900D03*
%TD*%
D15*
%TO.C,U6*%
X156750001Y-93147450D03*
X155800000Y-93147450D03*
X154849999Y-93147450D03*
X154849999Y-95852550D03*
X156750001Y-95852550D03*
%TD*%
D16*
%TO.C,U1*%
X151680000Y-100250000D03*
X151680000Y-99750000D03*
X151680000Y-99250000D03*
X151680000Y-98750000D03*
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X151680000Y-97750000D03*
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X151680000Y-96250000D03*
X151680000Y-95750000D03*
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X151680000Y-94750000D03*
D17*
X150250000Y-93320000D03*
X149750000Y-93320000D03*
X149250000Y-93320000D03*
X148750000Y-93320000D03*
X148250000Y-93320000D03*
X147750000Y-93320000D03*
X147250000Y-93320000D03*
X146750000Y-93320000D03*
X146250000Y-93320000D03*
X145750000Y-93320000D03*
X145250000Y-93320000D03*
X144750000Y-93320000D03*
D16*
X143320000Y-94750000D03*
X143320000Y-95250000D03*
X143320000Y-95750000D03*
X143320000Y-96250000D03*
X143320000Y-96750000D03*
X143320000Y-97250000D03*
X143320000Y-97750000D03*
X143320000Y-98250000D03*
X143320000Y-98750000D03*
X143320000Y-99250000D03*
X143320000Y-99750000D03*
X143320000Y-100250000D03*
D17*
X144750000Y-101680000D03*
X145250000Y-101680000D03*
X145750000Y-101680000D03*
X146250000Y-101680000D03*
X146750000Y-101680000D03*
X147250000Y-101680000D03*
X147750000Y-101680000D03*
X148250000Y-101680000D03*
X148750000Y-101680000D03*
X149250000Y-101680000D03*
X149750000Y-101680000D03*
X150250000Y-101680000D03*
%TD*%
M02*

888
FCB1010/FCB1010_controller/gerber/FCB1010_controller-F_Silkscreen.gbr Normal file
View File

@ -0,0 +1,888 @@
%TF.GenerationSoftware,KiCad,Pcbnew,9.0.2*%
%TF.CreationDate,2025-06-01T13:38:19+02:00*%
%TF.ProjectId,FCB1010_controller,46434231-3031-4305-9f63-6f6e74726f6c,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Legend,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 9.0.2) date 2025-06-01 13:38:19*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%ADD10C,0.100000*%
%ADD11C,0.040000*%
%ADD12C,0.120000*%
%ADD13C,0.152400*%
%ADD14C,0.127000*%
G04 APERTURE END LIST*
D10*
X145550000Y-104150000D02*
X149650000Y-104150000D01*
X145550000Y-103400000D02*
X149650000Y-103400000D01*
X147550000Y-102650000D02*
X147550000Y-104150000D01*
X148550000Y-102650000D02*
X148550000Y-104150000D01*
X145550000Y-102650000D02*
X145550000Y-104150000D01*
X149650000Y-102650000D02*
X145550000Y-102650000D01*
X146550000Y-102650000D02*
X146550000Y-104150000D01*
X149650000Y-104150000D02*
X149650000Y-102650000D01*
D11*
X145821428Y-102900991D02*
X145792857Y-102886705D01*
X145792857Y-102886705D02*
X145749999Y-102886705D01*
X145749999Y-102886705D02*
X145707142Y-102900991D01*
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X145678571Y-102929562D01*
X145678571Y-102929562D02*
X145664285Y-102958134D01*
X145664285Y-102958134D02*
X145649999Y-103015277D01*
X145649999Y-103015277D02*
X145649999Y-103058134D01*
X145649999Y-103058134D02*
X145664285Y-103115277D01*
X145664285Y-103115277D02*
X145678571Y-103143848D01*
X145678571Y-103143848D02*
X145707142Y-103172420D01*
X145707142Y-103172420D02*
X145749999Y-103186705D01*
X145749999Y-103186705D02*
X145778571Y-103186705D01*
X145778571Y-103186705D02*
X145821428Y-103172420D01*
X145821428Y-103172420D02*
X145835714Y-103158134D01*
X145835714Y-103158134D02*
X145835714Y-103058134D01*
X145835714Y-103058134D02*
X145778571Y-103058134D01*
X145964285Y-103186705D02*
X145964285Y-102886705D01*
X145964285Y-102886705D02*
X146135714Y-103186705D01*
X146135714Y-103186705D02*
X146135714Y-102886705D01*
X146278571Y-103186705D02*
X146278571Y-102886705D01*
X146278571Y-102886705D02*
X146350000Y-102886705D01*
X146350000Y-102886705D02*
X146392857Y-102900991D01*
X146392857Y-102900991D02*
X146421428Y-102929562D01*
X146421428Y-102929562D02*
X146435714Y-102958134D01*
X146435714Y-102958134D02*
X146450000Y-103015277D01*
X146450000Y-103015277D02*
X146450000Y-103058134D01*
X146450000Y-103058134D02*
X146435714Y-103115277D01*
X146435714Y-103115277D02*
X146421428Y-103143848D01*
X146421428Y-103143848D02*
X146392857Y-103172420D01*
X146392857Y-103172420D02*
X146350000Y-103186705D01*
X146350000Y-103186705D02*
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G01*
D14*
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G02*
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G75*
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G01*
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G75*
G02*
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G01*
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G75*
G02*
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G01*
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M02*

3682
FCB1010/FCB1010_controller/gerber/FCB1010_controller-In1_Cu.gbr Normal file
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File diff suppressed because it is too large Load Diff

3520
FCB1010/FCB1010_controller/gerber/FCB1010_controller-In2_Cu.gbr Normal file
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File diff suppressed because it is too large Load Diff

12
FCB1010/FCB1010_controller/gerber/FCB1010_controller-NPTH.drl Normal file
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M48
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148
FCB1010/FCB1010_controller/gerber/FCB1010_controller-PTH.drl Normal file
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M48
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T2
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M30

171
FCB1010/FCB1010_controller/gerber/FCB1010_controller-job.gbrjob Normal file
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{
"Header": {
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "9.0.2"
},
"CreationDate": "2025-06-01T13:38:19+02:00"
},
"GeneralSpecs": {
"ProjectId": {
"Name": "FCB1010_controller",
"GUID": "46434231-3031-4305-9f63-6f6e74726f6c",
"Revision": "rev?"
},
"Size": {
"X": 16.7,
"Y": 16.7
},
"LayerNumber": 4,
"BoardThickness": 1.6,
"Finish": "HAL lead-free",
"Castellated": true
},
"DesignRules": [
{
"Layers": "Outer",
"PadToPad": 0.01,
"PadToTrack": 0.01,
"TrackToTrack": 0.01,
"MinLineWidth": 0.1,
"TrackToRegion": 0.01,
"RegionToRegion": 0.01
},
{
"Layers": "Inner",
"PadToPad": 0.01,
"PadToTrack": 0.01,
"TrackToTrack": 0.01,
"MinLineWidth": 0.1,
"TrackToRegion": 0.01,
"RegionToRegion": 0.01
}
],
"FilesAttributes": [
{
"Path": "FCB1010_controller-F_Cu.gbr",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-In1_Cu.gbr",
"FileFunction": "Copper,L5,Inr",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-In2_Cu.gbr",
"FileFunction": "Copper,L7,Inr",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-B_Cu.gbr",
"FileFunction": "Copper,L4,Bot",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-F_Paste.gbr",
"FileFunction": "SolderPaste,Top",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-B_Paste.gbr",
"FileFunction": "SolderPaste,Bot",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-F_Silkscreen.gbr",
"FileFunction": "Legend,Top",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-B_Silkscreen.gbr",
"FileFunction": "Legend,Bot",
"FilePolarity": "Positive"
},
{
"Path": "FCB1010_controller-F_Mask.gbr",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "FCB1010_controller-B_Mask.gbr",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "FCB1010_controller-Edge_Cuts.gbr",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup": [
{
"Type": "Legend",
"Name": "Top Silk Screen"
},
{
"Type": "SolderPaste",
"Name": "Top Solder Paste"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Top Solder Mask"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "F.Cu"
},
{
"Type": "Dielectric",
"Thickness": 0.1,
"Material": "FR4",
"Name": "F.Cu/In1.Cu",
"Notes": "Type: dielectric layer 1 (from F.Cu to In1.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "In1.Cu"
},
{
"Type": "Dielectric",
"Thickness": 1.24,
"Material": "FR4",
"Name": "In1.Cu/In2.Cu",
"Notes": "Type: dielectric layer 2 (from In1.Cu to In2.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "In2.Cu"
},
{
"Type": "Dielectric",
"Thickness": 0.1,
"Material": "FR4",
"Name": "In2.Cu/B.Cu",
"Notes": "Type: dielectric layer 3 (from In2.Cu to B.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "B.Cu"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Bottom Solder Mask"
},
{
"Type": "SolderPaste",
"Name": "Bottom Solder Paste"
},
{
"Type": "Legend",
"Name": "Bottom Silk Screen"
}
]
}

15
FCB1010/FCB1010_controller/gerber/FCB1010_controller-top-pos.csv Normal file
View File

@ -0,0 +1,15 @@
Designator,Val,Package,Mid X,Mid Y,Rotation,Layer
"C1","100nF","C_0402",143.000000,-92.800000,180.000000,top
"C2","100nF","C_0402",151.500000,-102.500000,-90.000000,top
"C3","100nF","C_0402",143.500000,-102.500000,-90.000000,top
"C4","100nF","C_0402",153.400000,-96.300000,-90.000000,top
"C5","1uF","C_0402",152.000000,-93.000000,180.000000,top
"C6","1uF","C_0402",156.200000,-97.300000,180.000000,top
"C7","100nF","C_0402",153.400000,-98.300000,-90.000000,top
"J1","Conn_02x04_Odd_Even","X1321WVS-2x04J-C40D53",154.800000,-104.500000,-90.000000,top
"U1","STM32F042C6T6","QFP50P700X700X160-48N",147.500000,-97.500000,180.000000,top
"U2","TXU0104RUTR","PQFP12_RUT_TEX",147.000000,-105.500000,-90.000000,top
"U3","TXU0104RUTR","PQFP12_RUT_TEX",150.100000,-105.500000,-90.000000,top
"U4","TXU0104RUTR","PQFP12_RUT_TEX",143.900000,-105.500000,-90.000000,top
"U5","TXU0104RUTR","PQFP12_RUT_TEX",155.500000,-99.400000,0.000000,top
"U6","AP2112K-3.3TRG1","SOT_RG1_DIO",155.800000,-94.500000,-90.000000,top
1 Designator Val Package Mid X Mid Y Rotation Layer
2 C1 100nF C_0402 143.000000 -92.800000 180.000000 top
3 C2 100nF C_0402 151.500000 -102.500000 -90.000000 top
4 C3 100nF C_0402 143.500000 -102.500000 -90.000000 top
5 C4 100nF C_0402 153.400000 -96.300000 -90.000000 top
6 C5 1uF C_0402 152.000000 -93.000000 180.000000 top
7 C6 1uF C_0402 156.200000 -97.300000 180.000000 top
8 C7 100nF C_0402 153.400000 -98.300000 -90.000000 top
9 J1 Conn_02x04_Odd_Even X1321WVS-2x04J-C40D53 154.800000 -104.500000 -90.000000 top
10 U1 STM32F042C6T6 QFP50P700X700X160-48N 147.500000 -97.500000 180.000000 top
11 U2 TXU0104RUTR PQFP12_RUT_TEX 147.000000 -105.500000 -90.000000 top
12 U3 TXU0104RUTR PQFP12_RUT_TEX 150.100000 -105.500000 -90.000000 top
13 U4 TXU0104RUTR PQFP12_RUT_TEX 143.900000 -105.500000 -90.000000 top
14 U5 TXU0104RUTR PQFP12_RUT_TEX 155.500000 -99.400000 0.000000 top
15 U6 AP2112K-3.3TRG1 SOT_RG1_DIO 155.800000 -94.500000 -90.000000 top

188
FCB1010/FCB1010_controller/lib/AP2112K-3.3TRG1/2025-05-30_17-37-08.kicad_sym Normal file
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2724
FCB1010/FCB1010_controller/lib/AP2112K-3.3TRG1/SOT-25-5pin.stp Normal file
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557
FCB1010/FCB1010_controller/lib/AP2112K-3.3TRG1/footprints.pretty/SOT_RG1_DIO-L.kicad_mod Normal file
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557
FCB1010/FCB1010_controller/lib/AP2112K-3.3TRG1/footprints.pretty/SOT_RG1_DIO-M.kicad_mod Normal file
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533
FCB1010/FCB1010_controller/lib/AP2112K-3.3TRG1/footprints.pretty/SOT_RG1_DIO.kicad_mod Normal file
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980
FCB1010/FCB1010_controller/lib/TXU0104RUTR/footprints.pretty/PQFP12_RUT_TEX-M.kicad_mod Normal file
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767
FCB1010/FCB1010_controller/lib/TXU0104RUTR/footprints.pretty/PQFP12_RUT_TEX.kicad_mod Normal file
View File

@ -0,0 +1,767 @@
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945
FCB1010/FCB1010_controller/lib/W78C32C/W78C32C.kicad_sym Normal file
View File

@ -0,0 +1,945 @@
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961
FCB1010/FCB1010_controller/lib/W78C32C/footprints.pretty/W78C32C.kicad_mod Normal file
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498
FCB1010/FCB1010_controller/lib/X1321WVS-2x04J-C40D53/footprints.pretty/X1321WVS-2x04J-C40D53.kicad_mod Normal file
View File

@ -0,0 +1,498 @@
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15
FCB1010/FCB1010_controller/pick_and_place/FCB1010_controller-top-pos.csv Normal file
View File

@ -0,0 +1,15 @@
Designator,Val,Package,Mid X,Mid Y,Rotation,Layer
"C1","100nF","C_0402",143.000000,-92.800000,180.000000,top
"C2","100nF","C_0402",151.500000,-102.500000,-90.000000,top
"C3","100nF","C_0402",143.500000,-102.500000,-90.000000,top
"C4","100nF","C_0402",153.400000,-96.300000,-90.000000,top
"C5","1uF","C_0402",152.000000,-93.000000,180.000000,top
"C6","1uF","C_0402",156.200000,-97.300000,180.000000,top
"C7","100nF","C_0402",153.400000,-98.300000,-90.000000,top
"J1","Conn_02x04_Odd_Even","X1321WVS-2x04J-C40D53",154.800000,-104.500000,-90.000000,top
"U1","STM32F042C6T6","QFP50P700X700X160-48N",147.500000,-97.500000,180.000000,top
"U2","TXU0104RUTR","PQFP12_RUT_TEX",147.000000,-105.500000,-90.000000,top
"U3","TXU0104RUTR","PQFP12_RUT_TEX",150.100000,-105.500000,-90.000000,top
"U4","TXU0104RUTR","PQFP12_RUT_TEX",143.900000,-105.500000,-90.000000,top
"U5","TXU0104RUTR","PQFP12_RUT_TEX",155.500000,-99.400000,0.000000,top
"U6","AP2112K-3.3TRG1","SOT_RG1_DIO",155.800000,-94.500000,-90.000000,top
1 Designator Val Package Mid X Mid Y Rotation Layer
2 C1 100nF C_0402 143.000000 -92.800000 180.000000 top
3 C2 100nF C_0402 151.500000 -102.500000 -90.000000 top
4 C3 100nF C_0402 143.500000 -102.500000 -90.000000 top
5 C4 100nF C_0402 153.400000 -96.300000 -90.000000 top
6 C5 1uF C_0402 152.000000 -93.000000 180.000000 top
7 C6 1uF C_0402 156.200000 -97.300000 180.000000 top
8 C7 100nF C_0402 153.400000 -98.300000 -90.000000 top
9 J1 Conn_02x04_Odd_Even X1321WVS-2x04J-C40D53 154.800000 -104.500000 -90.000000 top
10 U1 STM32F042C6T6 QFP50P700X700X160-48N 147.500000 -97.500000 180.000000 top
11 U2 TXU0104RUTR PQFP12_RUT_TEX 147.000000 -105.500000 -90.000000 top
12 U3 TXU0104RUTR PQFP12_RUT_TEX 150.100000 -105.500000 -90.000000 top
13 U4 TXU0104RUTR PQFP12_RUT_TEX 143.900000 -105.500000 -90.000000 top
14 U5 TXU0104RUTR PQFP12_RUT_TEX 155.500000 -99.400000 0.000000 top
15 U6 AP2112K-3.3TRG1 SOT_RG1_DIO 155.800000 -94.500000 -90.000000 top

7
FCB1010/FCB1010_controller/sym-lib-table Normal file
View File

@ -0,0 +1,7 @@
(sym_lib_table
(version 7)
(lib (name "W78C32C")(type "KiCad")(uri "${KIPRJMOD}/lib/W78C32C/W78C32C.kicad_sym")(options "")(descr ""))
(lib (name "TXU0104RUTR")(type "KiCad")(uri "${KIPRJMOD}/lib/TXU0104RUTR/2025-05-30_16-08-53.kicad_sym")(options "")(descr ""))
(lib (name "STM32F042C6T6")(type "KiCad")(uri "${KIPRJMOD}/lib/STM32F042C6T6/STM32F042C6T6.kicad_sym")(options "")(descr ""))
(lib (name "AP2112K-3.3TRG1")(type "KiCad")(uri "${KIPRJMOD}/lib/AP2112K-3.3TRG1/2025-05-30_17-37-08.kicad_sym")(options "")(descr ""))
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56
FCB1010/pinmap.txt Normal file
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@ -0,0 +1,56 @@
1 NIC* => NC
2 P1.0/T2 => IC12 P1 => ADC /CS
3 P1.1/T2EX => IC12 P6 => ADC DO
4 P1.2 => IC12 P5 => ADC REF
5 P1.3 => NC
6 P1.4 => NC
7 P1.5 => X19 P13 => Buttons 6-10 Select
8 P1.6 => X20 P14 => Buttons 1-5 Select
9 P1.7 => NC
10 RST => IC7 P6 => Power good
11 P3.0/RxD => X18 P3 => MIDI RX
12 NIC* => NC
13 P3.1/TxD => IC4 P9 => MIDI TX
14 P3.2/INT0 => NC?
15 P3.3/INT1 => NC?
16 P3.4/T0 => IC6 P6, IC12 P7 => ADC CLK
17 P3.5/T1 => IC6 P5
18 P3.6/WR => IC14 P27
19 P3.7/RD => IC14 P22
20 XTAL2 => XTAL
21 XTAL1 => XTAL
22 VSS => GND
23 NIC* => NC
24 P2.0/A8 => IC14 P25
25 P2.1/A9 => IC14 P24
26 P2.2/A10 => IC14 P21
27 P2.3/A11 => IC14 P23
28 P2.4/A12 => IC14 P2
29 P2.5/A13 => IC13 P26
30 P2.6/A14 => IC14 P1
31 P2.7/A15 => IC5 P5
32 PSEN => IC13 P20
33 ALE => ?
34 NIC* => NC
35 EA/VPP => GND
36 P0.7/AD7 => IC13 P19
37 P0.6/AD6 => IC13 P18
38 P0.5/AD5 => IC13 P17
39 P0.4/AD4 => IC13 P16
40 P0.3/AD3 => IC13 P15
41 P0.2/AD2 => IC13 P13 => (Latched by IC9) Decoder A2
42 P0.1/AD1 => IC13 P12 => (Latched by IC9) Decoder A1
43 P0.0/AD0 => IC13 P11 => (Latched by IC9) Decoder A0
44 VCCA => VCC
IC3: 74HC273D Octal D-type flip-flop
IC4: 74HC04D Hex inverter
IC5: 74hc138D 3-to-8 line decoder/demultiplexer; inverting
IC6: ATMLH716 ?EEPROM?
IC7: 7705AC Supply-Voltage Supervisor
IC8: W78C032C microcontroller
IC9: 74HC373D Octal D-type transparent latch; 3-state
IC10: 74HC273D Octal D-type flip-flop
IC11: 74HC273D Octal D-type flip-flop
IC12: C0832C 8-Bit Analog to Digital Converter
IC14: KM62256C 64k x 8bit SRAM